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Not much of a pattern in the non-0.7Vp-p ones so far. Samsung and Dell account for a large number of them, but they account for a large number of monitors of that era generally. Maybe manufacturing date?...

Not really! There are EDIDs from monitors manufactured in 2022 that request 1V p-p output! What the hell?

One awk script later, date seems irrelevant: from 1995 through 2022 manufacturing dates, 0.7Vp-p and 1Vp-p monitors are represented in approximately equal amounts in the EDID database. Certainly same order of magnitude. Which I find completely bemusing for several reasons, one being: wait people are still _making_ new analog monitors??

more scripts later, no obvious pattern other than the monitors advertising 1Vp-p seem cheaper and nastier, which makes me wonder if there's some popular legacy VGA decoder chip that they all slap on the board to get an extra port to sell and that chip just doesn't give a fuck?

Hahaha wait no, I have a better, much worse theory.

They're all reporting the 1Vp-p variant that ranges -0.300V to 0.700V. Which is the bit value `000` in EDID.

My new theory is those monitors just didn't bother setting a value in that field, because the monitor worked fine with the default so who cares.

Which, yeah, it does, because they also all specify "blank level equals black level", meaning the pixel data swings 0V through 0.7V, with -0.3V being used only for sync pulses.

... But modern graphics cards don't send composite sync pulses on the pixel lines, they all use separate TTL wires for those. So, the -0.3 to 0.7 and 0 to 0.7 EDID values are functionally identical in practice, as long as your EDID also tells the sender that "Separate" sync signals are supported. Which these EDIDs all do.

Some of the monitors advertise that they will understand sync pulses sent on separate wires, or in the NTSC-style composite form, or in the "Sync on Green" form where the green analog line behaves differently to red and green.

But most say they only understand separate sync signals. Making the advertisement of supporting full 1Vp-p swings irrelevant, because they then immediately say "oh but I don't understand the thing you'd do with 0.3V of that range, so, uh, I guess 0.7Vp-p really"

Assuming no sync pulses on the color lines, and assuming black==blank, then in practice the GPU is driving 0V to 0.7V outputs, and that's either exactly what the monitor wants, or for the very rare monitors using the NTSC voltage levels, it's a teeny bit shy of the nominal 0.714V high level, but still well within tolerance so who cares.

Okay I'm going to stop dissecting VGA now, I promise I'm done. I can pop one layer back up the stack, compute resistors for the VGA DAC.

@ewenmcneill 5% either way should be fine, probably 10% also. It's very sloppy.

IBM themselves don't seem to have ever specified tolerances, but some manufacturers of 3p VGA DACs did... In a roundabout way, so I'm in the middle of mathing out what voltage tolerances they translate to.

@danderson that makes sense.

Also assuming there’s an external cable involved, the two connectors and the 1-2M of cable will have some resistance. So outputting, eg, 0.725V might well still be received at under/much closer to 0.700V. (And I suspect in practice some monitors probably have an AGC on their input connections for this reason, if only to boost to their internal ADC’s preferred range.)

@ewenmcneill Some datasheets I've seen guesstimate 0.7-0.9 ohms for the cable. But with all the series/parallel reductions, the change in load impedance is dwarfed by the tolerances on the main transmission line termination impedance (2%, so 73.5 to 76.5 ohms)

@ewenmcneill That's sort of the weirdness. IBM specifies 0.7V nominal with no tolerance, but the later ICs all describe a current DAC, and effectively coach you to configure it such that the full white current level, when pushed into a 75 ohm transmission line, comes out to 0.7V-ish.

But they specify tolerances on the transmission line impedance and the current outputs and the reference current resistor... So I can turn that into error bars for the voltage, once I confirm the exact topology.

@ewenmcneill Many hours later: based on the specs of the ADV7125 RGB DAC, and making a bunch of assumptions about components, it will produce an effective max voltage of 698mV ±27mV (±3.87%)

That's a modern part with modern tolerances, so the receiving monitor needs to be more lax than that. Based on that, I think hitting 700mV ±5% should be quite safe, and I wouldn't be surprised if ±10% works more than not.

@ewenmcneill That's with some very 90s tolerances in places though. I read somewhere, though can't find it now, that the transmission line was 75 ohms ±5%. Combined with a ±1% voltage reference in the DAC and a ±1% configuration resistor, you get the figures above.

If you assume a transmission line that's more like 1%, then the voltage this DAC produces is ±1.7%. It's producing a relatively precise constant current, so it's heavily dependent on the variance in the transmission line impedance.

@ewenmcneill Either way, from experience tinkering with this generator so far, hitting ±1-2% tolerance on the voltage is pretty easy, if you use 1% resistors. And that gets you in the same tolerance ballpark as the Analog Digital ICs that professionals use. More than good enough for unprofessional use.